1. Field
Example Embodiments relate to a memory integrated circuit device, and for example, to a memory integrated circuit device that includes MOS transistors whose operation speeds may be improved due to the decreasing of their threshold voltages at lower temperatures.
2. Description of Related Art
With the development of semiconductor manufacturing technology, the memory density of memory integrated circuit devices has rapidly increased of late. The increase of memory density may cause power consumption of memory integrated circuit devices to increase. One method of reducing the power consumption of memory integrated circuit devices is to lower power supply voltages used in the memory integrated circuit devices.
A memory integrated circuit device may include a plurality of MOS transistors. The threshold voltage VT of each of the MOS transistors and the power supply voltage VDD of the memory integrated circuit device may have the relationship expressed in Formula 1:VDD≧(3×VT)  (1)
FIG. 1 is an example graph of a threshold voltage of a MOS transistor with respect to the temperature of the memory integrated circuit device. Referring to FIG. 1, if the power supply voltage VDD is lower, the threshold voltage of the MOS transistor may increase as the temperature decreases.
A conventional method to lower the threshold voltage of a NMOS transistor provides a temperature independent constant current source that provides a constant current through a diode thereby producing a voltage drop across a diode. The voltage drop of the diode is temperature dependent, for example the voltage drop of the diode decreases as a temperature of the diode increases. The voltage drop across the diode is applied to a first input of a summing circuit and a constant reference voltage output from a temperature independent constant voltage source is applied to a second input of the algebraic summing circuit. The logic circuit is designed to operate at a predetermined temperature, and the magnitude of the reference voltage may be chosen to equal the magnitude of the voltage drop of the diode when the diode is at the predetermined temperature. Accordingly, an output of the summing circuit is output as a NMOS back bias voltage based on the temperature of the diode.
A conventional method to lower the threshold voltage of a PMOS transistor provides a temperature independent constant current source that provides a constant current to a resistor. The temperature coefficient of the resistor is positive, and the resistor's resistance increases with increasing temperature. The current flowing through the resistor produces a voltage drop which is supplied to a first input of a summing circuit. A second input of the summing circuit is coupled to ground. The constant current source and resistor are predetermined such that, at equilibrium, the voltage drop of the resistor is substantially equal to a supply voltage of the logic circuit when the logic circuit is operating at its nominal temperature. Accordingly, an output of the summing circuit is output as PMOS back bias based on the temperature of the resistor.
However, these conventional methods use means for increasing or decreasing the back bias voltage of a MOS transistor at a specific normal temperature, for example, 85° C., as its starting point but do not disclose means for improving the characteristics of the back bias voltage of the MOS transistor at a lower temperature (e.g., a sub-zero temperature). Moreover, the conventional art does not disclose means for changing the back bias voltage of the MOS transistor at all temperatures in a range of a higher temperature to a lower temperature.
Memory integrated circuit devices may not only be used at a normal temperature but may also be occasionally used at a higher temperature and a lower temperature. In a conventional memory integrated circuit device, the threshold voltage of a MOS transistor that uses a lower power supply voltage VDD sharply increases at a lower temperature, so that the operating speed of the conventional memory integrated circuit device may be decreased. In addition, the threshold voltage of the MOS transistor may be lower at a higher temperature, so that leakage current may increase compared with that at a normal temperature.